This invention relates to digital integrated circuits which use non-overlapping clock signals, and more particularly to altering timing relationships of clock signals in a microprocessor, particularly during testing of the microprocessor.
During the process of creating a new integrated circuit design, a circuit is typically designed and validated by simulation, a layout of the circuit is created, masks are made, and a prototype integrated circuit is fabricated. At this point, some of the prototype circuits are tested. Occasionally, a prototype part will not be completely functional due to a timing problem within the integrated circuit. If the timing problem creates a set-up or a hold time failure in one or more latch circuits, then the prototype circuit may be difficult or impossible to completely test.
In another case, two or more design teams may be contributing portions of a circuit design to form a complete, complex integrated circuit. One team may use a library of pre-designed circuits to design a portion of the integrated circuit, and another team may use a different library of pre-designed circuits to design a different portion of the integrated circuit. If the two different design libraries have different timing parameter assumptions, then the prototype part may be inoperable.
In yet another case, it may be desirable to operate an integrated circuit at temperatures or voltages that are outside of the intended operating range. In such an environment, circuit timing constraints often render an integrated circuit inoperable.
An object of the present invention is to provide a way to overcome setup and hold time problems in a prototype integrated circuit.
Another object of the present invention is to provide a way to overcome set-up and hold time problems during extended range operation of an integrated circuit.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
In general, and in a form of the present invention, a method for operating an integrated circuit that has a plurality of latches which operate in response to set of non-overlapping clock signals, is provided. A non-overlap time value is selected by setting a control signal to a first value. An internal master clock signal is formed in response to an input clock signal. The master clock is used to latch registers within the integrated circuit. An internal slave clock is formed in a non-overlapping manner and used for driving signals from the internal registers. The driving edge of the slave clock is delayed from the latching edge of the slave clock in accordance with the non-overlap time parameter.
In another form of the present invention, a second value for non-overlap time is selected by setting the control signal to a second value.
Other embodiments of the present invention will be evident from the description and drawings.